• Towards the Functional Verification of Large Sequential Circuits
  C.A.J. van Eijk, J.A.G. Jess

• A Verification Methodology Mixing Model Checking and Symbolic Trajectory Evaluation
  R. Raimi and M. Pandey

• Efficient Verification of Combinational Circuits Using Local BDDs and a Hash Table
  R. Mukherjee, J. Jain, K. Takayama, M. Fujita, J.Abraham, D. Fussell

• Verification of Combinational Circuits Using Conjunctively Decomposed Implications
  H. Shin, G. Hachtel

• Functional Simulation Using Binary Decision Diagrams
  C. Scholl, R. Drechsler, B. Becker

• CAD-MARK 97: Benchmarking and Analysis of Architectures for CAD Applications
  A. Mehrotra, S. Qadeer, R. Ranjan, R. Katz
  

• Approximate Timing Analysis Under the XBD0 Model
  Y. Kukimoto, W. Gosti, A. Saldanha, R. Brayton

• CLP-Based Gate-Level Timing Verification with Delay Correlation
  S.M. Aourid, E. Cerny
  

• Statistical Delay Calculation
  M. Berkelaar

• Hierarchical Timing Analysis Under the XBD0 Model
  Y. Kukimoto, R. Brayton

• Retiming of Edge-Triggered Circuits with Multiple Clocks and Load Enables
  C. Legl, P. Vanbekbergen, A. Wang

• Delay Fault Testing of Asynchronous Sequential Circuits
  M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Saldanha,
  A. Taubin
  

12:30-1:30 LUNCH

1:30-2:30 SESSION 3: PASS TRANSISTOR LOGIC (and more)

• Domino Logic Synthesis and Technology Mapping
  M. Prasad, D. Kirkpatrick, R. Brayton, A. Sangiovanni-Vincentelli

• On Synthesizing Pass Transistor Networks
  P. Buch, A. Narayan, A. Newton, A. Sangiovanni-Vincentelli

• Decision Diagrams and Pass Transistor Logic Synthesis
  V. Bertacco, S. Minato, P. Verplaetse, L. Benini, G. DeMicheli

• Projective Solutions to Boolean Equations and the Boolean Matching Problem
  M. Escobar, F. Somenzi

• Multiport Register File Using Wave Pipelining
  K. Takano, T. Sasaki, N. Oba, H.Kobayashi, T. Nakamura

• Performance Optimization by Path Selection
  S. Cremoux, T. Mommier, J.L. Guntzel, N. Azemard, D, Auvergne

• Technology Dependent Timing Optimization
  H. Savoj, A. Domic

• Evaluation of Path Mapping for Delay Optimization
  Y. Tamiya

• Telescoping Units; A New Paradigm for Performance Optimization of VLSI Designs
  L. Benini, G. DeMicheli, E. Macii, M. Poncino

• A Divide and Conquer Strategy for Hazard Free 2-Level Logic Synthesis
  J.W. Rutten, M.A. Kolsteren

• Performance Analysis of an Arbiter Using Probabilistic Time Petri Nets
  M. Escalante, L. Lavagno, N. Dimopoulos

• Synthesis of Externally Synchronous, Internally Asynchronous Circuits
  B. Tabbara, L. Lavagno, A. Sangiovanni-Vincentelli

• Using Gate Sizing to Reduce Glitch Power
  E. Jacobs, M. Berkelaar

• Trace Driven Logic Synthesis-Application to Power Minimization
  L. Carloni, P. McGeer, A. Saldanha, A. Sangiovanni-Vincentelli

• On-Going Research on Address Bus Encoding for Low Power: A Status Report
  L. Benini, G. DeMicheli, E. Macii, M. Poncino, Q. Quer,
  D. Sciuto, C. Silvano

• Rewiring for Power Optimization
  P. Buch, C. Lennard, A. Newton
  

3:30-4:30 SESSION 4: COMBINATIONAL SYNTHESIS TECHNIQUES

• Improvements in Technology Independent Optimization of Logic Circuits
  H. Savoj

• Layout Driven Delay Optimization With Logic Re-Synthesis
  T. Ishioka, M. Murofushi, M. Murakata

• An Integrated Placement and Synthesis Approach for Timing Closure of Power PC Microprocessors
  S. Hojat, P. Villarrubia

• An Exact Solution to Simultaneous Technology Mapping and Linear Placement Problem for Trees
  J. Lou, A. Salek, M. Pedram

8:00-10:00 Panel: "Synthesis tools for deep submicron designs: requirements and prospects"

Moderator: Massoud Pedram

7:30-8:30 BUFFET BREAKFAST

8:30-9:30 SESSION 5: BDDS

• Minimization of BDDs by Evolutionary Algorithms R. Drechsler, N. Gockel
  

• Partitioned BDDs vs. Other BDD Models
  B. Bollig, I. Wegener

• Canonical TBDDs and Their Application to Combinational Verification
  E. Goldberg, Y. Kukimoto, R. Brayton

• Speeding Up Variable Reordering of OBDDs
  C. Meinel, A. Slobodova
  

• Rid-Grasp Redundancy Identification and Removal Using Grasp
  J. Kim, J.M. Silva, H. Savoj, K. Sakallah

• Synthesis for Full Testability of Partitioned Combinational Circuits Using Boolean Differential Calculus
  B. Steinbach, Z. Zhang

• Coloring Real-Life Graphs
  O. Coudert

• Solving Covering Problems Using LPR-Based Lower Bounds
  S. Liao, S. Devadas

• Improving Satisfiability Algorithms with Dominance and Partitioning
  J. Marques Silva, A.L. Oliveira

• A New Method for Escaping Local Minima in in Two-Level Minimization
  E. Goldberg, R. K. Brayton

• Secure Implementation of Decision Diagrams
  R. Drechsler

• Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions
  R. Ranjan, W. Gosti, R. Brayton, A. Sangiovanni-Vincentelli

• Remembrance of Things Past: Locality and Memory in BDDs
  S. Manne, D. Grunwald, F. Somenzi

• Linear Sifting of Decision Diagrams
  C. Meinel, F. Somenzi, T. Theobald

• Technology Mapping for Storage Elements Based on BDD Matching
  J-H Yi, S.H. Hwang

• Synthesis of Timed Circuits Using BDDs
  R. Thacker, C. Myers
  

10:30-11:30 SESSION 6: SATISFIABILITY AND COVERING TECHNIQUES

• Implementing Boolean Satisfiability in Configurable Hardware
  P. Zhong, M. Martonosi , S. Malik, P. Ashar

• A Sat-Based Implication Engine for Efficient Derivation of Indirect Implications
  P. Tafertshofer, C. Ebner, A. Ganz, M. Henftling

• Negative Thinking in Search Methods: Application to Unate Covering
  E. Goldberg, L Carloni, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli

• On Computing Minimum Size Prime Implicants
  J. Marques Silva
  

12:30-1:30 LUNCH

1:30-2:30 SESSION 7: SEQUENTIAL SYNTHESIS

• A Synthesis Procedure for Flexible Autonomous Finite-State Machines
  I. Pomeranz, S. M. Reddy

• Sequential Circuit Optimization by FSM Transformation
  S. Park, K. Choi

• A Symbolic Algorithm for Low-Power Sequential Synthesis
  B. Kumthekar, I-H Moon, F. Somenzi

• An Exact Formulation of the BDD Input Encoding Problem
  W. Gosti, T. Villa, A. Saldanha, A. Sangiovanni-Vincentelli

• The Library Free Technology Mapping Problem
  A. Reis, R. Reis, D. Auvergne, M. Robert

• A New Method for the Approximate Computation of Observability Relations
  A. Kolbl, B. Wurth

• Optimizing Designs Containing Black Boxes
  T. H. Liu, K. Sajid, A. Aziz, V. Singhal

• Partial Extraction of Equivalent States for Optimizing Large Sequential Circuits
  H. Higuchi, Y. Matsunaga

• Synthesis of Digital Circuits and Its Acceleration Using Genetic Algorithms
  F. Burchert, A. Falkenberg, M. Koch, D. Tavangarian

• Optimization of Sequential Circuits Without Global Resets By Structural Transformations
  Q. Wang, S.B.K. Vrudhula

• Universal Finite State Machines and Environment Modeling
  R. Raimi and R. Hojati

• Sequential Optimization Without State Space Exploration
  R. Brayton, A. Mehrotra, S. Qadeer, V. Singhal

• High-Order Temporal Effects in Finite State Machine Analysis
  D. Marculescu, R. Marculescu, M. Pedram

• Support Minimization Based State Assignment
  A. Crews, F. Brewer

• Retiming-Based Factorization for Multi-level Logic Optimization
  S. Bommu, M. Ciesielski, N. O'Neill, P. Kalla

• Theory and Algorithms for Face Hypercube Embedding
  E. Goldberg, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli