| Wednesday, June 2 |
| 12:00 - 1:00 : Lunch |
| 1:30 - 2:50 : Power and Area
Driven Logic Synthesis chair: Michel Berkelaar |
| Accurate Keeper Sizing using ADD-based Models of Subthreshold Leakage
Saswat Bohidar, Kundan Nepal, and R. Iris Bahar |
| Topology Dependent Synthesis for Reduced Leakage Prabhakar Kudva, Leon Sigal, and Hans Jacobson |
| Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
Valavan Manohararajah, Stephen D. Brown, and Zvonko G. Vranesic |
| LUT FPGA Technology Mapping for Area Minimization with Optimum Depth
Maxim Teslenko and Elena Dubrova |
| 2:50 - 3:35 : Poster Session 1 |
| On the Minimization of Longest Path Length for Decision Diagrams
Shinobu Nagayama and Tsutomu Sasao |
| On Placement and Sizing of Sleep Transistors in Leakage Critical
Circuits Vishal Khandelwal and Ankur Srivastava |
| Efficient Computation and Representation of Double-Vertex Dominators
in Circuit Graphs Maxim Teslenko and Elena Dubrova |
| ViewCut: An Exploratory Environment for Analyzing Maximal-Volume
Bounded Cutsets in a DAG David E. Wallace |
| Enhanced Multi-Level Clustering for Combinational Circuits
Wei-Zhi Ye, Tzong-Shing Liu, and Ting-Chi Wang |
| Design of an Application-Specific PLD Architecture Jae-Jin Lee and Gi-Yong Song |
| Modeling and Synthesis of Multi-rail Multi-protocol QDI Circuits
Vivian Bregier, Bertrand Folco, Laurent Fesquet, and Marc Renaudin |
| Automatic Layout Synthesis Based Performance Optimization
Alexis Landrault, Nadine Azemard, Philippe Maurine, Michael Robert, and Daniel Auvergne |
| Fault Localization in Reversible Circuits Is Easier than for Classical
Circuits Kavitha Ramasamy, Radhika Tagare, Edward Perkins, and Marek Perkowski |
| Clockless Implementation Structure and Methodology for DSM
Implementation Yinghua Li, Alex Kondratyev, and Robert K. Brayton |
| Addressing the Effects of Reconvergence on Placement-Coupled Logic
Replication Milos Hrkic and John Lillis |
| Reversible Logic Circuit Synthesis Based on a New Complexity Measure
Pawel Kerntopf |
| Post-Placement Functional Decomposition for FPGAs Valavan Manohararajah, Deshanand P. Singh, Stephen D. Brown, and Zvonko G. Vranesic |
| An Iterative Technique for Improved Two-level Logic Minimization
Kunal R. Shenoy, Nikhil S. Saluja, and Sunil P. Khatri |
| Super-Set of Permissible Functions Katsunori Tanaka and Yahiko Kambayashi |
| FZQSAT: A QSAT Solver for QBFs in Prenex NNF (A Useful Tool for
Circuit Verification) Mohammad GhasemZadeh, Volker Klotz, and Christoph Meinel |
| A Constraint Solver Based on Word-Level Decision Diagrams
Yirng-An Chen and Shen-Wei Huang |
| Logic Synthesis for Layout Regularity using Decision Diagrams
Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jin S. Zhang, and Marek Perkowski |
| 3:35 - 4:55 : Layout-Aware and
Post-Layout Synthesis chair: Prabhakar Kudva |
| Layout-Aware Logic Decomposition Satrajit Chatterjee and Robert K. Brayton |
| Technology Mapping with Pre-layout Wire Length Prediction
Qinghua Liu and Malgorzata Marek-Sadowska |
| Wave Pipelining for Interconnect Arvind Vidyarthi and Soha Hassoun |
| Properties of Maximal-Volume Bounded Cutsets in a DAG
David E. Wallace |
| 4:55 - 6:00 : Focus Group
Discussions chair: Etienne Jacobs |
| Thursday, June 3 |
| 7:30 - 8:30 : Breakfast |
| 8:30 - 9:50 :
Verification chair: Mukul Prasad |
| Functional Dependency for Verification Reduction Jie-Hong Roland Jiang and Robert K. Brayton |
| A Partitioning Methodology for BDD-based Verification
Debashis Sahoo, Subramanian Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, and E. Allen Emerson |
| Invariant Checking Combining Forward and Backward Traversal
Christian Stangier and Thomas Sidle |
| Dynamic Transition Relation Simplification for Bounded Property
Checking Andreas Kuehlmann |
| 9:55 - 10:40 : Poster Session 2 |
| An Intermediate Level HDL for System Level Design Jean Pierre David and Etienne Bergeron |
| Synthesis of Secure FPGA Implementations Kris Tiri and Ingrid Verbauwhede |
| Bug Localization of Hardware System with Control Flow Distance
Minimization ShengYu Shen, Ying Qin, and Si-Kun Li |
| Blockage-aware Buffer Insertion with Adaptive Routing Tree
Re-construction Zhong-Ching Lu and Ting-Chi Wang |
| Decomposition of BDDs with Application to Physical Mapping of Regular
PTL Circuits Aiqun Cao and Cheng-Kok Koh |
| A Range-Based BDD Minimization Algorithm Qiushuang Zhang, Zhihong Zeng, and Maciej Ciesielski |
| FSM Re-Engineering for Low Power State Encoding Lin Yuan and Gang Qu |
| Extracting Data Flow Model from von Neumann Program for Synthesis
Chien-Wei Li, Hong-Seok Kim, and Wen-mei W. Hwu |
| Reversible Conservative Elementary Cellular Automata (ECA) Circuits
and their Quantum Computation Anas Al-Rabadi and William Feyerherm |
| On the Construction of Zero-deficiency Parallel Prefix Adders
Haikun Zhu, Chung-Kuan Cheng, and Ronald Graham |
| Functional Vectors Generation for RTL Descriptions Based on Path
Enumeration and Constraint Logic Programming Tun Li, Yang Guo, and Si-Kun Li |
| Simultaneous Floorplanning and Binding: A Probabilistic Approach
Azadeh Davoodi and Ankur Srivastava |
| Switch-Box and Connection-Box for Segmented Interconnection in
Hierarchical FPGA Xiaojun Ma, Bo Wang, and Jiarong Tong |
| A Novel Approach for Identifying False Paths Felipe Marques, Renato Ribas, and Andre Reis |
| An Efficient Equivalence Checking of Similar C Descriptions with Use
of the Textual Difference Takeshi Matsumoto, Hiroshi Saito, and Masahiro Fujita |
| Synthesis of Reversible Circuits from a Subset of Muthukrishnan-Stroud
Quantum Realizable Multi-Valued Gates Nicholas Denler, Bruce Yen, Marek Perkowski, and Pawel Kerntopf |
| Effects of Property Ordering in an Incremental Formal Modeling
Methodology Syed Suhaib, Deepak Mathaikutty, and Sandeep Shukla |
| System Level Partitioning for Programmable Platforms Using the Ant
Colony Optimization Gang Wang, Wenrui Gong, and Ryan Kastner |
| A Transformation Based Algorithm for Ternary Reversible Logic
Synthesis using Universally Controlled Ternary Gates Erik Curtis and Marek Perkowski |
| 10:40 - 12:00 : SAT and Model
Checking chair: Christian Stangier |
| SAT-Based Complete Don't-Care Computation for Network Optimization
Alan Mishchenko and Robert K. Brayton |
| Restoring Circuit Structure from SAT Instances Jarrod A. Roy, Igor L. Markov, and Valeria Bertacco |
| Incrementally improving SAT-based Bounded Model Checking
Liang Zhang, Mukul R. Prasad, and Michael S. Hsiao |
| Approximate Symbolic Model Checking for Incomplete Designs
Tobias Nopper and Christoph Scholl |
| 12:00 - 1:00 : Lunch |
| 1:00 - 2:30 : Focus Group
Discussions chair: Etienne Jacobs |
| 2:30 - 4:10 : Sequential
Synthesis and Optimization chair: Stephen Edwards |
| A New Efficient Retiming Algorithm Derived by Formal Manipulation
Hai Zhou |
| Performance and Area Optimization using Sequential Flexibility
Christoph Albrecht, Pascal Witte, and Andreas Kuehlmann |
| Efficient Solution of Language Equations using Partitioned
Representations Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, and Nina Yevtushenko |
| Composition Operators in Language Equations Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alan Mishchenko, and Alberto L. Sangiovanni-Vincentelli |
| Automated Pipelining in ASIC Synthesis Methodology: Gate Transfer
Level Alexandre Smirnov, Alexander Taubin, and Mark Karpovsky |
| 4:10 - 5:00 : Poster Session 3: For first 16 presentations (before Thursday noon) |
| 5:00 - 6:30 : Invited Session:
Computation & Biological Systems: New Frontiers for EDA chair: Mukul Prasad |
| Evolution as the Blind Engineer: Wiring Minimization in the Brain
Dr. Dmitri Chklovskii, Cold Spring Harbor Laboratory |
| abstract The human brain is a network containing hundred billion neurons, each communicating with several thousand others. Neuronal communications are implemented by biological wiring, which draw on limited resources such as space, time and energy. This suggests that evolution must have solved VLSI-design-like problems. We analyzed multiple features of brain architectures and found that they could be explained as solutions to optimal design problems. We found examples of optimization in component placement, branched routing, overcoming wiring congestion, and interconnect width variation. Such approach leads to a systematic view of the brain architecture, which should help understand brain function. |
| bio Dmitri ``Mitya'' Chklovskii (born 1969) received his Ph.D. in theoretical physics from MIT in 1994. He became interested in neurobiology while being a Junior Fellow at the Harvard Society of Fellows. He trained in neurobiology as a Sloan Fellow with C. F. Stevens at the Salk Institute. In 1999 he founded the Theoretical Neurobiology group at Cold Spring Harbor Laboratory. His research is aimed at understanding basic principles of brain design. He is known for successful application of constrained optimization to neuronal circuits. |
| Computational Biology: Trends and Challenges in Computing
Dr. Ajay Royyuru, IBM T. J. Watson Research Center |
| abstract The intersection of information technology and biology is amongst the most exciting and challenging areas for research, steadily transforming biology from a top-down descriptive science to a quantitative bottom-up integrative science. This talk will provide an overview of computational biology with examples of biology driven needs in computing, covering the spectrum from data driven computing needs in bioinformatics, to the compute intensive large scale simulations in biology. |
| bio Ajay Royyuru heads the Computational Biology Center at IBM Research, with 35 researchers engaged in various research projects including bioinformatics, structural biology, protein science and applications on Blue Gene, functional genomics, and systems biology. Ajay joined IBM Research in 1998, initiating research in structural biology. He obtained his PhD in Molecular Biology from the Tata Institute of Fundamental Research, Mumbai in 1993 and then did post-doctoral work in structural biology at Memorial Sloan-Kettering Cancer Center, New York. Prior to joining IBM he spent 2 years developing structural biology software at Accelrys. His current research interests are in understanding sequence-structure-function relationships in proteins and is actively involved in protein structure prediction, protein folding, and structural genomics. Ajay has over 30 research publications in structural and computational biology. |
| Friday, June 4 |
| 7:30 - 8:30 : Breakfast |
| 8:30 - 10:10 : Advances in
Logic Synthesis chair: Elena Dubrova |
| Fast Computation of Generalized Symmetries in Boolean Functions
Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, and Jerry R. Burch |
| Optimization Methods in Look-Up Table Rings Tsutomu Sasao, Masaki Kusano, and Munehiro Matsuura |
| Comparing Two Rewiring Models Subarna Sinha, Xinning Wang, and Robert K. Brayton |
| Timing Analysis of Cyclic Combinational Circuits Marc D. Riedel and Jehoshua Bruck |
| On Breakable Cyclic Definitions Jie-Hong Roland Jiang, Alan Mishchenko, and Robert K. Brayton |
| 10:10 - 10:55 : Coffee Break/Poster Session 4: For last 17 presentations (after Thursday noon) |
| 11:00 - 12:00 : Emerging Topics
in Synthesis chair: Stephen A. Edwards |
| Logic Synthesis Preserving High-Level Specification
Eugene Goldberg |
| Optimal Synthesis of Linear Reversible Circuits Ketan N. Patel, Igor L. Markov, and John P. Hayes |
| Is Quantum Search Practical? George F. Viamontes, Igor L. Markov, and John P. Hayes |
| 12:00 - 1:00 : Lunch |
| 1:30 - 3:15 : Focus Group
Presentations chair: Etienne Jacobs |
| 3:15 - 4:00 : Coffee Break/Poster Session 5: Open to all |
| 4:00 - 5:20 : Advances in
System Synthesis chair: Timothy Kam |
| Optimizing Polynomial Expressions by Factoring and Eliminating Common
Subexpressions Anup Hosangadi, Farzan Fallah, and Ryan Kastner |
| Fetch Halting on Critical Load Misses Brian Singer, Nikil Mehta, R. Iris Bahar, and Richard Weiss |
| C to Asynchronous Dataflow Circuits: An End-to-End Toolflow
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea, and Seth Copen Goldstein |
| The Challenges of Hardware Synthesis from C-like Languages
Stephen A. Edwards |