 2016 Co-located with the Design Automation Conference 
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25th International Workshop on Logic & Synthesis June 10 – 11, 2016 Thompson Conference Center — Austin, TX
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Our sponsors
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| IWLS 2016 Program |
| Friday June 10, 2016 |
| 8:00am - 8:30am: Welcome Breakfast |
| 8:30am - 9:00am: Workshop Opening
Rolf Drechsler and Andre Reis |
| 9:00am - 10:30am: Special Session on Emerging Technologies Session Chair: Robert Wille |
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Biochemistry Synthesis on Digital Microfluidic Biochips
Krishnendu Chakrabarty (Duke University, USA) |
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Photonic Design Automation: Old Wine in New Bottle?
Priyank Kalla (University of Utah, USA) |
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Reversible Circuits: Application and Design Challenges
Rolf Drechsler (University of Bremen/DFKI GmbH, Germany) |
| 10:30am - 11:00am: Break |
| 11:00am - 12:30am: Session 1 - SAT-Based Approaches |
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Fast Generation of Lexicographic Satisfiable Assignments: Enabling Canonicity in SAT-based Applications
Ana Petkovska (EPFL, Switzerland), Alan Mishchenko (UC Berkeley, USA), Mathias Soeken and Giovanni De Micheli (EPFL, Switzerland), Robert Brayton (UC Berkeley, USA) and Paolo Ienne (EPFL, Switzerland) |
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Progressive Generation of Canonical Sums of Products Using a SAT Solver
Ana Petkovska (EPFL, Switzerland), Alan Mishchenko (UC Berkeley, USA), David Novo (LIRM Montpellier, France), Muhsen Owaida (ETH Zurich, Switzerland) and Paolo Ienne (EPFL, Switzerland) |
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SAT-based Functional Dependency Computation
Mathias Soeken (EPFL, Switzerland), Pascal Raiola (University of Freiburg, Germany), Baruch Sterin (UC Berkeley, USA) and Matthias Sauer (University of Freiburg, Germany) |
| 12:30am - 1:45pm: Lunch |
| 1:45pm - 3:15pm: Session 2 - Word-Level Abstraction and Sequential Optimization |
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Identifying Transparent Logic in Gate-Level Circuits
Yu-Yun Dai and Robert Brayton (UC Berkeley, USA) |
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Uninterpreted Function Abstraction and Refinement for Word-level Model Checking
Yen-Sheng Ho, Alan Mishchenko and Robert Brayton (UC Berkeley, USA) |
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Analysis of Incomplete Circuits using Dependency Quantified Boolean Formulas
Ralf Wimmer, Karina Wimmer, Christoph Scholl and Bernd Becker (University of Freiburg, Germany) |
| 3:15pm - 3:30pm: Break |
| 3:30pm - 4:30pm: Poster Session |
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Physical Design Factors that contribute to Routing Congestion in Monolithic 3D Integrated Circuits
Yosef Borga and Daniel Limbrick (NC A&T State University, USA) and Sung Kyu Lim (Georgia Institute of Technology, USA) |
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A Fast Analytic Approach to the Collapsing and Verification of Threshold Logic Circuits
Nian-Ze Lee and Jie-Hong Roland Jiang (National Taiwan University, Taiwan) |
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Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines
Chun-Hong Shih and Jie-Hong Roland Jiang (National Taiwan University, Taiwan) |
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SystemCDG - AI Based Coverage Driven Stimuli Generation for SystemC
Jannis Stoppe, Arved Friedemann and Rolf Drechsler (University of Bremen, Germany) |
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Graphene Logic Synthesis using a Constructive Approach
Mayler Martins (Carnegie Mellon University, USA) |
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Patent Interpretation using Boolean Logic and Venn Diagrams
Simone Reis (UAB, Spain), Andre Reis (UFRGS, Brazil), Jordi Carrabina and Pompeu Casanovas (UAB, Spain) |
| 4:30pm - 5:30pm: Session 3 - Asynchronous Circuits |
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Hybrid Synchronous-Asynchronous Tool Flow for Emerging VLSI Design
Filipp Akopyan, Carlos Tadeo Ortega Otero and Rajit Manohar (Cornell University, USA) |
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Fluid Pipelines: Elastic Circuitry without Throughput Penalty
Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Skinner and Jose Renau (UC Santa Cruz, USA) |
| 5:30pm - 6:30pm: Keynote 1 |
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Amorphous Data-parallelism
Keshav Pingali, UT Austin |
| 6:30pm - 8:30pm: Dinner |
| Saturday June 11, 2016 |
| 8:00am - 8:30am: Welcome Breakfast |
| 8:30am - 10:00am: Session 4 - Technology Mapping |
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LUT Mapping and Optimization for Majority-Inverter Graphs
Winston Haaswijk, Mathias Soeken and Giovanni De Micheli (EPFL, Switzerland) |
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Inversion Minimization in Majority-Inverter Graphs
Eleonora Testa and Mathias Soeken (EPFL, Switzerland), Luca Amarú (Synopsys Inc., USA), Pierre-Emmanuel Gaillardon and Giovanni De Micheli (EPFL, Switzerland) |
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Versatile SAT-based Remapping for Standard Cells
Alan Mishchenko and Robert Brayton (UC Berkeley, USA), Thierry Besson, Sriram Govindarajan, Harm Arts and Paul van Besouw (Mentor Graphics, USA) |
| 10:00am - 10:30am: Break |
| 10:30am - 11:30am: Session 5 - Map Reduce / Circuit Testing |
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Boosting the Performance of MapReduce Applications via Distributed Accelerators on a Chip-Multiprocessor
Abraham Addisie and Rawan Abdel-Khalek (University of Michigan, USA), Ritesh Parikh (Intel, USA) and Valeria Bertacco (University of Michigan, USA) |
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Approximate Identification of Sink Strongly-Connected Components for the Generation of Close-to-Functional Broadside Tests
Irith Pomeranz (Purdue University, USA) |
| 11:30am - 12:30am: Keynote 2 |
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Design Automation Challenges in Neuromorphic Systems
Rajit Manohar, Cornell University |
| 12:30am - 1:30pm: Lunch |
| 1:30pm - 3:00pm: Session 6 - Stochastic and Statistical Methods |
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A Branch-and-Bound-Based Minterm Assignment Algorithm for Synthesizing Stochastic Circuit
Xuesong Peng and Weikang Qian (Shanghai Jiao Tong University, China) |
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A Deterministic Approach to Stochastic Computation
Devon Jenson and Marc Riedel (University of Minnesota, USA) |
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Decomposition of Index Generation Functions Using a Monte Carlo Method
Tsutomu Sasao (Meiji University, Japan) and Jon Butler (Naval Postgraduate School, USA) |
| 3:00pm - 3:15pm: Closing Remarks Rolf Drechsler |
| 3:15pm - 3:45pm: Goodbye Break and Planning of IWLS 2017 |