2019

28th International Workshop
on Logic & Synthesis

June 21 – 23, 2019

EPFL — Lausanne, Switzerland

EPFL


IWLS 2019 Technical Program


Friday June 21


8:50am - 9:00am: Workshop Opening


9:00am - 10:00am: Keynote 1: Logic Synthesis Challenges in EDA Industry
Patrick Vuillod, Synopsys, France
Session Chair: TBD


10:00am - 10:30am: Coffee Break


10:30am - 12:00pm: Session 1: New Bounds and Minimum Circuits for Logic Optimization
Session Chair: TBD
The Complexity of Self-Dual Monotone 7-Input Functions
Eleonora Testa, Winston Haaswijk, Mathias Soeken and Giovanni De Micheli (EPFL, Switzerland)
An Improved Bounds on the Number of Variables to Represent Index Generation Functions using Linear Decompositions
Tsutomu Sasao (Meiji University, Japan)
Enumeration of Minimum Circuit Structures
Siang-Yun Lee, Jie-Hong R. Jiang (National Taiwan University, Taiwan), Alan Mishchenko, Robert Brayton (UC Berkeley, USA)


12:00pm - 1:00pm: Lunch Break


1:00pm - 2:00pm: Session 2: Specialized Optimization: QBF and IIG Functions
Session Chair: TBD
Quantifier Localization for DQBF
Aile Ge-Ernst, Christoph Scholl and Ralf Wimmer (University of Freiburg, Germany)
On Irreducible Index Generation Functions
Tsutomu Sasao, Kyu Matsuura and Yukihiro Iguchi (Meiji University, Japan)


2:00pm - 3:00pm: Coffee Break + Poster Session (part 1)
Efficiently mapping applications to heterogeneous systems
Hiwot Kassa, Tarunesh Verma, Todd Austin and Valeria Bertacco (University of Michigan, USA)
Parallel Combinational Equivalence Checking
Vinicius Possani, (UFRGS, Brazil) Alan Mishchenko, (UC Berkeley, USA) Renato Ribas and Andre Reis (UFRGS, Brazil)
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits
Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große and Rolf Drechsler (University of Bremen, Germany)
A Simple BDD Package without Variable Reordering and Its Application to Logic Optimization with Permissible Functions
Yukio Miyasaka, (University of Tokyo, Japan) Alan Mishchenko (UC Berkeley, USA) and Masahiro Fujita (University of Tokyo, Japan)
Defect-Tolerance CMOL Mapping Optimization Based on Defective Cell Reuse
Yinshui Xia and Xiaojing Zha (Ningbo University, China)


3:00pm - 4:30pm: Session 3: Synthesis for Quantum and Approximate Computing
Session Chair: TBD
ROS: Resource constrained oracle synthesis for quantum computers
Giulia Meuli, Mathias Soeken, Martin Roetteler and Giovanni De Micheli (EPFL, Switzerland)
Automatic Preparation of Uniform Quantum States Utilizing Boolean Functions
Fereshte Mozafari, Mathias Soeken and Giovanni De Micheli (EPFL, Switzerland)
Advanced Ordering Search for Multi-Level Approximate Logic Synthesis
Chang Meng, Paul Weng, Sanbao Su and Weikang Qian (University of Michigan-Shanghai Jiao Tong University Joint Institute, China)


4:30pm - 4:50pm: IWLS 2019 Programming Contest: Legal AIGs


4:50pm - 5:00pm: Update on new EPFL best results


Saturday June 22


8:30am - 9:30am: Keynote 2: How Designing Machine Learning Hardware Can Go Wrong, and What To Do About It
Bryan Bowyer, Mentor, a Siemens Business, USA
Session Chair: TBD


9:30am - 10:30am: Session 4: Advances in Majority and Threshold Logic Synthesis
Session Chair: TBD
Searching Parallel Separating Hyperplanes for Effective Threshold Logic Function Compression
Siang-Yun Lee, Nian-Ze Lee and Jie-Hong Roland Jiang (National Taiwan University, Taiwan)
Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs
Walter Lau Neto, Xifan Tang, Max Austin, (University of Utah, USA) Luca Amaru (Synopsys Inc., USA) and Pierre-Emmanuel Gaillardon (University of Utah, USA)


10:30am - 11:00am: Coffee Break


11:00am - 12:00pm: Session 5: Circuit and Design Considerations in Synthesis
Session Chair: TBD
Automated Timing Constraint Generation for Pulse Gate Circuits
David McCarthy, Merritt Miller and Forrest Brewer (UCSB, USA)
Automatic Conversion from Flip-flop to 3-phase Latch-based Designs
Huimei Cheng, Yichen Gu and Peter Beerel (USC, USA)


12:00pm - 1:30pm: Lunch Break


1:30pm - 2:30pm: Keynote 3: Algebra, Proofs and Multipliers
Armin Biere, Johannes Kepler University, Austria
Session Chair: TBD


2:30pm - 3:30pm: Session 6: More Multipliers!
Session Chair: TBD
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification Tools
Alireza Mahzoon, Daniel Grosse and Rolf Drechsler (University of Bremen, Germany)
Searching for best Karatsuba recurrences
Cagdas Calik, Morris Dworkin, Nathan Dykas and Rene Peralta (NIST, USA)


3:30pm - 4:30pm: Coffee Break + Poster Session (part 2)
Efficiently mapping applications to heterogeneous systems
Hiwot Kassa, Tarunesh Verma, Todd Austin and Valeria Bertacco (University of Michigan, USA)
Parallel Combinational Equivalence Checking
Vinicius Possani, (UFRGS, Brazil) Alan Mishchenko, (UC Berkeley, USA) Renato Ribas and Andre Reis (UFRGS, Brazil)
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits
Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große and Rolf Drechsler (University of Bremen, Germany)
A Simple BDD Package without Variable Reordering and Its Application to Logic Optimization with Permissible Functions
Yukio Miyasaka, (University of Tokyo, Japan) Alan Mishchenko (UC Berkeley, USA) and Masahiro Fujita (University of Tokyo, Japan)
Defect-Tolerance CMOL Mapping Optimization Based on Defective Cell Reuse
Yinshui Xia and Xiaojing Zha (Ningbo University, China)


4:00pm - 5:30pm: Session 7: Dataflow Optimization and CNN Based Synthesis
Session Chair: TBD
Performance Optimization of Dataflow Circuits
Lana Josipovic, Andrea Guerrieri, Paolo Ienne (EPFL, Switzerland) and Jordi Cortadella (UPC, Spain)
Towards a Novel Logic Synthesis Framework Supervised by Convolutional Neural Network
Max Austin, Walter Lau Neto, (University of Utah, USA) Luca Amaru, (Synopsys Inc., USA) Xifan Tang and Pierre-Emmanuel Gaillardon (University of Utah, USA)


5:30pm - 5:40pm: Closing Remarks