| Wednesday, June 4 |
| 1:15 - 2:15 : Timing Estimation and Optimization |
| Global Delay Optimization using Structural Choices Alan Mishchenko, Robert Brayton, and Stephen Jang |
| A Network-Flow Based Cell Sizing Algorithm Shantanu Dutt and Huan Ren |
| Performance Estimation with Automatic False-Path Detection for
System-Level Designs Daisuke Ando, Tasuku Nishihara, Takeshi Matsumoto, and Masahiro Fujita |
| 2:30 - 3:30 : Arithmetic and Cryptographic Circuit Synthesis |
| NLFSR Re-Synthesis for High Throughput Elena Dubrova |
| Integrating Common Sub-expression Elimination with Algebraic Methods
for Polynomial System Synthesis Sivaram Gopalakrishnan and Priyank Kalla |
| XP^2: A New Compact Representation for Manipulating Arithmetic
Circuits Ajay Verma, Philip Brisk, and Paolo Ienne |
| 3:30 - 4:30 : Poster Session |
| Structural Metrics for Congestion Driven Logic Synthesis
Andrew Ling, Jianwen Zhu, and Stephen Brown |
| Equivalence-checking for Reversible Circuits Shigeru Yamashita and Igor Markov |
| SynECO: Technology Remapping With Incremental Constrained Placement
and Exact Timing Estimation Anuj Kumar and Azadeh Davoodi |
| A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt
Assignment and Continuous Gate Sizing Tai-Hsuan Wu, Lin Xie, and Azadeh Davoodi |
| A new algorithm to solve synchronous FSM equations Nina Yevtushenko, Svetlana Tikhomirova, and Tiziano Villa |
| The Synthesis of Stochastic Logic to Perform Multivariate Polynomial
Arithmetic Weikang Qian and Marc Riedel |
| Subthreshold and Gate Leakage Estimation in Complex Gates
Paulo Butzen, Leomar da Rosa, Erasmo Chiappetta Filho, Dionatan Moura, Andre Reis, and Renato Ribas |
| Performance Estimation and Slack Matching for Pipelined Asynchronous
Architectures with Choice Gennette Gill, Vishal Gupta, and Montek Singh |
| Power Study of a 1000-Core Processor Fuat Keceli, Tali Moreshet, and Uzi Vishkin |
| 5:00 - 6:00 : Invited Talk (I) |
| Software and System Synthesis for Venture-Backed Success
Juan-Antonio Carballo |
| Thursday, June 5 |
| 9:00 - 10:00 : Sequential Synthesis and Resynthesis |
| Scalable and Scalably-Verifiable Sequential Synthesis
Alan Mishchenko, Michael Case, Robert Brayton, and Stephen Jang |
| Retiming and Resynthesis with Sweep Are Complete for Sequential
Transformation Nikolaos Liveris and Hai Zhou |
| FPGA Area Reduction by Multi-Output Function Based Sequential
Resynthes Yu Hu, Victor Shi, Rupak Majumdar, and Lei He |
| 10:15 - 11:15 : Satisfiability and Decomposition |
| The Analysis of Cyclic Circuits with Boolean Satisfiability
John Backes, Brian Fett, and Marc Riedel |
| Low-latency SAT Solving on Multicore Processors with Priority
Scheduling and XOR Partitioning Stephen Plaza, Igor Markov, and Valeria Bertacco |
| Boolean Factoring and Decomposition of Logic Networks
Alan Mishchenko, Robert Brayton, and Satrajit Chatterjee |
| 11:30 - 12:30 : Programming Competition |
| Global Flow Optimization in OAGear Tobias Welp and Nathan Kitchen |
| Mapping and Resynthesis for LUT-based FPGAs with an Efficient
SAT-Based Boolean Matching Victor Shih, Yu Hu, Lei He, and Rupak Majumdar |
| Truss: A User-Friendly Platform for Industrial-Scale EDA Research
Donald Chai |
| 2:00 - 2:45 : Invited Talk (II) |
| A Simple DNA Gate Motif for Synthesizing Large-scale Circuits
Lulu Qian |
| 3:00 - 4:00 : Potpourri (I) |
| Synthesis with External Don't-Cares Using Shannon Entropy and Craig
Interpolation Kai-hui Chang, Valeria Bertacco, Igor Markov, and Alan Mishchenko |
| Efficient Symmetry-based Circuit Rewiring for Placement Optimization
Donald Chai and Andreas Kuehlmann |
| On-the-fly modeling for synthesizing multi-clock SVA
Jiang Long, Andrew Seawright, and Paparao Kavalipati |
| 4:15 - 5:15 : Boolean Matching and Technology Mapping |
| Boolean Matching for Incompletely Specified Functions Using Satisfy
Counts Afshin Abdollahi |
| On the Decreasing Significance of Large Standard Cells in Technology
Mapping Jae-sun Seo, Igor Markov, Dennis Sylvester, and David Blaauw |
| Templates and Algorithms for Fault Tolerant Boolean Matching in FPGAs
Yu Hu, Zhe Feng, Rupak Majumdar, and Lei He |
| 6:30 - 7:30 : Invited Talk (III) over dinner |
| The Power of Procrastination Jorge Cham |
| Friday, June 6 |
| 9:00 - 10:00 : Invited Talk (IV) |
| Genetic Design Automation: Progress and Future Research Directions
Chris Myers |
| 10:15 - 11:15 : Potpourri (II) |
| Module Locking in Biochemical Synthesis Brian Fett and Marc Riedel |
| Correct-by-construction Microarchitectural Pipelining
Timothy Kam, Michael Kishinevsky, Jordi Cortadella, and Marc Galceran |
| On the Numbers of Variables to Represent Sparse Logic Functions
Tsutomu Sasao |
| 11:30 - 12:30 : Verification |
| Recording Synthesis History for Sequential Verification
Alan Mishchenko and Robert Brayton |
| Hardware-Accelerated Formal Verification Hiroaki Yoshida, Satoshi Morishita, and Masahiro Fujita |
| Cut-Based Inductive Invariant Computation Michael Case, Alan Mishchenko, and Robert Brayton |